Transmission Gate Based 8T SRAM Cell for Biomedical Applications

Abstract

There is an immense necessity for several kB of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMS dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Biomedical applications eliminating the use of peripheral circuitry during the read operation. This topology offers a smaller area, reduced delay, low power consumption, and improved data stability in the read operation. Static Random Access Memories mostly contribute to the performance, area, and power dissipation of digitally integrated systems. The mentioned implantable and wireless applications require low-power circuits operating for a long time, occupying less area without degrading the performance, as it provides inconvenience and may even be risky especially while considering the implantable devices.

Introduction

I. INTRODUCTION

Static random-access memory is a type of semiconductor memory that uses bistable latching circuitry to store each bit. The term static differentiates it from dynamic RAM which must be periodically refreshed. SRAM exhibits data remembrance but is still volatile in a conventional sense, that data is eventually lost when memory is not powered. The continuous scaling down of bulk CMOS creates major issues due to its base material. The primary obstacles to the scaling of bulk CMOS to 32nmgatelengths include short channel effects Sub-threshold leakage gate-dielectric leakage and device-to-device variations.  Due to the sudden increase in threshold voltage ie. Vt oscillation produced by overall and general process variations occur in ultra-short channel devices, 6T SRAM cell and their modifications cannot be operated at advance scaling of supply voltages without functional and parametric failure causing yield loss. The design of a standard 6T SRAM cell undergoes a lot of problems with write delay. The design of Low power 6T SRAM cell could decrease the write power and access delay but could not improve their stability. In deep submicron ranges, none of the earlier works has studied about the improvement of variability in SRAM cells at the schematic level.

II. EXISTING SRAM’S

In SRAMS, the memory cell is a basic element as it occupies a significant portion of the area. Implementation of the 6T SRAM cell is very simple as depicted in Fig 1. The cell is well structured with two pass transistors and two cross-coupled inverters. The two cross-coupled inverters form a simple latch capable of accumulating one bit of the data. The two Pass transistors are connected with the two complementary types of Bit Lines (BL and BL Bar) and a Word Line (WL), providing a connection between the cell and the outside world. SRAMS usually operates in three states namely Read, Write, and Hold.

Conclusion

In this paper, Cadence virtuoso tool along with 45nm technology is used to observe the behaviors of different types of SRAM. This design provides a virtuous improvement in Delay and Area. This proposed work enlarges the overall performance of the system by reducing complexity and cost. By analyzing overall performance, the proposed SRAM has more advantages. The Speed is also improved to some extent from the existing SRAMs.

References

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Copyright

Copyright © 2023 Mr. C. Laxmana Sai, B. Rohith, G. Rithik, L. Vivek Vardhan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.